1. Field of the Invention
The invention relates to a gate turn-off thyristor having uniform current, low impedance and ultra-low gate impedance differential to all parts of the device.
2. Description of the Related Art
Conventional Gate Turn-off thyristors (GTO) are made with large feature sizes and emitters that are defined by deep silicon etches. Those GTOs are designed to accommodate large gate currents that flow in the gate metalization in turn-off and so that the gates are not shorted to the cathode when packaged in the standard hockey puck (or PressPak) package. Advanced GTOs having fine linewidths can be made in modern wafer fabrication facilities. However, providing low inductance and resistance gate contacts to all parts of the devices has not been previously shown as is done in the present invention.
High voltage GTO or SCR based systems are expensive due to package and assembly costs and the cost of gate drives. In addition, those high voltage GTO or SCR based systems have only marginal device performance. The packages are large, must be clamped at thousands of pounds of pressure, and have large inductances. Even though the devices can be cooled on two sides, that cooling is greatly degraded because the heat conducts across several dry interfaces. Due to the cost and yield of silicon, high voltage thyristor structures are used for the largest current and highest voltage applications.
PressPak packaging is difficult and expensive to effectively combine MOS-type devices with GTOs, especially where parasitic gate inductance and resistance are key to performance. One packaging alternative is to modify the power module in their high power IGBT modules. One technique presently used to build high-current and high-voltage IGBTs (Insulated Gate Bipolar Transistors) is to attach the bottom surfaces of many discrete IGBT chips in parallel on a common collector electrode on a heat sink, and to attach parallel gate and emitter electrodes to their top surfaces, using wire bonding or soldered electrodes, and to assemble these into a larger module package.
Another technique is to begin with many small devices, each already assembled in its own small package, and to connect these in parallel in a larger module package. In those packages, thermal resistance is approximately the same as for the PressPak package. Dry interfaces are eliminated, a thinner path is provided to the heat sink, and the heat source is distributed, i.e., there are several parallel die. However, one-sided cooling is provided, which is not as effective as two-sided cooling. Nonetheless, an overall lower thermal impedance is achieved over the PressPak packaging.
An example of the PressPak packaging is shown, for instance, in FIG. 1. The device is a monolithic full silicon wafer, rather than a number of discrete individual chips in parallel. The silicon wafer may be in the range of 25 to 40 mils thick and 2-6 inches in diameter. This wafer is hard-soldered or brazed to a refractory metal such as tungsten or molybdenum which has a coefficient of thermal expansion close to that of silicon, with a thickness of around 100 mils and a diameter just slightly larger than that of the silicon wafer. The silicon-plus-metal disc is then placed between two copper pole-pieces that provide electrical and thermal contact to both sides of the disc. The pole pieces that press against the disc are flat and polished, and are firmly held together by an electrically insulating structure, so they press toward each other, against opposite sides of the disc with high pressure to assure good thermal contact.
ThinPak technology is a power semiconductor packaging technique developed by Silicon Power Corporation. The ThinPak packaging technique eliminates wire bonds, results in near 100% power module yields, reduces parasitics by an order of magnitude, and simplifies module manufacturing so that it can be automated as a simple pick and place operation.
Present GTO devices have large feature size, primarily due to the need for a high current gate that is formed by etching into silicon about 10-15 microns. When the pole piece is clamped to the top surface, the emitter fingers are contacted while the recessed gate is brought out to an external gate contact. GTO finger width is typically 25 mils (or about 600 microns), and finger length is about 200 mils.
GTOs have been made having a turn-off effected by discrete FET chips packaged inside a PressPak packaged GTO which are gated to effectively short the GTO gate and cathode. Both 53 and 77 mm devices have been produced with voltages as high as 9000 volts. This greatly reduces the cost and size of the turn-off gate drive. Compared to an MCT, in which the FET is built into every cell, a larger area die than a MOS gated device is achieved. A high voltage MOS gated device is obtained without taking all of the silicon through both the FET and the HV GTO processes.
In principle, a sufficient number of FETs can be paralleled to turn off any current. In practice, however, the amount of current that can be turned off is governed by the worst GTO finger-to-gate FET circuit inductance, which, for a high performance device, must be in the nano-henry gate inductance range and the sub-nanohenry gate differential inductance region. If the inductance can be made to approach zero, then the turn-off is dominated by 1) GTO finger current uniformity, and 2) the finger width and upper base sheet resistance under the GTO fingers. Finger sizes of the order of those found in planar transistors, (i.e., instead of 20 to 30 mil finger repeat distances 2 to 3 mils) have been used to increase the theoretical maximum current that can be turned off. The difficulty here is that this small geometry is not compatible with the traditional close tube approach in which the fingers are defined by a deep etch and the cathode pressure contacted.
Another shortcoming of the conventional devices is that they do not interdigitate high current gate and cathode contacts with very small (microns) separation. Yet another problem is that they cannot achieve a stable, high voltage breakdown voltage without the normal deep, closed tube diffusion. A GTO and bipolar transistor is needed that can be made with planar geometries and MOSFET-like cell sizes that are packaged to allow high current contacts to die areas as small as several mils on a side equally well to both gate and cathode in a GTO or emitter in a transistor.